This invention relates to a FIFO module, and a deskew circuit and a rate matching circuit having the same.
The continuing demand for higher speed network connections has resulted in the development of the 10-Gigabit Fiber Channel (10 GFC) and 10-Gigabit Ethernet (10 GbE) networks. In a 10 GbE network, between the media access control (MAC) layer and the physical (PHY) layer, there is a 10-Gigabit Media Independent Interface (XGMII). The XGMII provides full duplex operation at a rate of 10 Gb/s between the MAC and the PHY layers. Each direction of operation is independent of the other and involves 32 bits of data, as well as clock and control signals to define a 74-bit interface between the MAC and the PHY layers.
To overcome issues related to routing such a large number of signals of the 74-bit interface over a distance of more than 7 cm, the 10-Gigabit Attachment Unit Interface (XAUI) was developed. XAUI is a full duplex interface that uses four self-clocked serial differential links in each direction of operation to achieve a 10 Gb/s data rate. Each serial link operates at 3.125 Gb/s to accommodate both data and the overhead associated with 8B/10B coding. The self-clocked nature of the coding eliminates skew concerns between clock and data, and extends the functional reach of the XGMII to approximately 50 cm. Conversion between the XGMII and XAUI interfaces occurs at the XGMII extender sublayer (XGXS).
The transmit and the receive path of the XGMII interface is each organized into four lanes. Each lane uses 8 bit data signals and a 1 bit control signal. At the source side of the XAUI interface, the data for transmission on a given lane as well as a timing clock are converted into a self-clocked, serial, 8B/10B encoded data stream. Each encoded data stream is transmitted across a single differential link to a destination side in frames or packets. At the destination side, the clock is recovered from the incoming data stream. The incoming data is decoded and then mapped back to the 32-bit XGMII format. Thus the 74 pin wide XGMII interface is reduced to a XAUI interface that uses 8 differential pairs for supporting the 8 serial differential links, requiring a total of only 16 pins.
The frames in each lane are separated by inter-frame or inter-packet periods, which are intervals during which no data transmission occurs. The XGMII sends idle control characters during these periods instead. In 10 GbE terms, these periods are known as Inter-Packet Gaps (IPGs). During the IPGs, XGXS converts XGMII idle control characters to and from a randomized sequence of control code-groups to enable serial lane synchronization, clock rate compensation (also known as rate matching) and lane-to-lane alignment (also known as deskewing). This randomized sequence includes control codegroups commonly referred to “A”, “K” and “R” codegroups.
A “K” or synchronization codegroup in the data stream enables a XAUI receiver at the receiving side to attain codegroup synchronization on the incoming bit stream. Each lane adjusts for proper alignment to the “K” codegroup whenever it appears. Codegroup synchronization is considered to be achieved on each lane upon reception of four consecutive error free and valid “K” codegroups for the respective lane.
Each serial transmission lane, however, operates independently of the other lanes. Data streams transmitted on a lane can often go out of alignment with respect to data streams transmitted on the other lanes due to different path delays and latencies between the lanes. This misalignment is known as lane-to-lane skew. Lane alignment or deskewing is accomplished by use of the “A” or alignment codegroup. The XGXS defines specific times during the IPG when an “A” codegroup should be present on each of the four lanes, simultaneously. The receiver uses these “A” codegroups to correct lane to lane skew. Correcting lane to lane skew is known as deskewing.
Furthermore, the XGXS compensates for clock rate differences in clock domains that often exist between the transmitting side and the receiving side of a link. By monitoring the difference between incoming and outgoing data rates, the receiver can add or delete “R” or skip codegroups in the IPG to balance or rate match the incoming and the outgoing data rates in each lane.
Typically, a receiver implemented as an application specific integrated circuit (ASIC) includes prior art FIFO modules that are connected to respective deserializers. The prior art FIFO modules are used for buffering data streams received on their respective lanes. Each of the FIFO modules has two pointers—a write pointer and a read pointer. The write pointer points to or addresses memory locations in the FIFO module for writing codegroups in the data stream thereto. The read pointer, which trails the write pointer during operation, points to or addresses memory locations that were previously written to, to allow the codegroups stored therein to be read for further processing.
In order to perform deskewing and rate matching, additional circuits external to the FIFO modules are required in the receiver. These additional circuits include register banks for further buffering read codegroups and comparators for comparing read codegroups with predetermined codegroups etc. Such a design suffers from a variety of disadvantages. Firstly, the chip area of the ASIC is not utilized efficiently due to the need for the additional circuits. The degree of inefficiency depends on how long it takes to compare the read codegroups with the predetermined codegroups, and the number of register banks that are required on the chip is directly proportional to the comparison duration. Hence, the longer the comparison duration, the higher the degree of chip area inefficiency. The hardware structure of the ASIC is thus non-deterministic, as the structure will need to be changed in accordance with the comparison duration.
Secondly, the ASIC would have to be verified at a system level for any change in the additional circuits. Such verification is complicated to perform and is time consuming. Thirdly, deskewing is performed only after control codegroups stored in the FIFO modules are read and made available outside of the FIFO modules. When a memory location is written to, the memory location is read only when the read pointer is advanced to point to that particular memory location. There is therefore a lag between the writing and the reading of a particular memory location, and deskewing can only be done after a control codegroup is read from the memory location. Deskewing is therefore delayed, and rate matching, which is performed after deskewing, is similarly delayed.